In VLIW processors, multiple short instruction words (SIWs) are typically executed in parallel to provide high performance. It is possible to have multiple instructions within a VLIW simultaneously target the same register within a register file. This simultaneous targeting produces a conflict situation. One of the ways hardware typically deals with the situation is by treating the conflicting instructions as a no-operation (nop) and indicating an error has occurred, or by indicating an error situation exists and assigning priorities to the instructions to control which single instruction wins in writing to the conflicting target register. When the conflict “hazard” occurs, it usually means an error situation has occurred and typically no advantage can be found in the situation.